1. Field of the Invention
This invention relates to floating gate memory devices such as EEPROMs and more specifically to techniques for decoding control signals and for providing signal voltages for the erase, program and read functions of negative-gate-erase FLASH EEPROM arrays.
2. Prior Art
There is a class of non-volatile memory devices known as negative-gate-erase FLASH electrically erasable read only memory (EEPROM) devices. A key feature of FLASH EEPROM technology is having memory storage cells which are relatively small in size. Small size is obtained by either eliminating a select gate or by merging a select gate into a cell as is a split-gate structure. Further elimination of a byte select transistor for a memory cell requires that the erase mode, which is obtained by lowering the gate threshold voltage V.sub.t of a cell, operates on a group of cells called a sector or a page. Principle objectives in designing a FLASH memory device are to obtain the smallest die area, the smallest sector size, the simplest die-fabrication process, and either a large or small sector size, depending upon the applications of the memory device.
Negative gate erase schemes are used for erasing EEPROMS because they provide a more reliable and scaleable method for lowering the threshold voltage V.sub.t of a memory cell. A significant drawback of prior art negative gate erase schemes for EEPROMS is their inability to multiplex, or switch, both positive and negative voltages from central voltage sources to a word line or to a control gate while still keeping the sector sizes small. For prior art implementations which use standard twin-well fabrication processes, erase sector sizes have typically been limited to 64K bytes for 4M flash devices. This limitation is due to the requirement that each sector must have its own separate negative charge pump.
Another significant drawback of prior art negative gate erase schemes occurs when the supply voltage is reduced. At lower voltages, the efficiency of charge pumps are reduced and, consequently, larger dedicated negative charge pumps are required for each sector. Using one large dedicated charge pump per sector limits a sector to a specific group of word lines or control gates. A typical charge pump is either ON to provide -13 volts, OFF to provide +5 volts, or disconnected.
FIG. 1 shows a prior art system 100 for providing the operating voltages for a negative-gate erase FLASH EEPROM array. In this approach, each of n memory sectors requires a Separate, dedicated large local negative charge pump, typically shown as 102, 104, to generate the voltages required to separately drive the word lines or control gates for the individual sectors of the EEPROM array. In this approach, the EEPROM array is divided into a number n of separate large sectors and a single negative charge pump is dedicated to drive only a particular one of those sectors.
On the left side of the Figure is an X decoder and multiplexer circuit 105 which provides for switching between a positive voltage VZMS provided at a terminal 106 and a decoded row select signal XIN provided at a terminal 108. XIN is used during a normal "read" mode of operation and during a "program" mode of operation. XIN goes between 0 and VCC. XIN designates which row is to be read or programmed and function as a Row Select signal.
VZMS is used for reading or during a programming operation. VZMS is either at VCC, the power supply level, during a normal read mode or at some high voltage which is used during the programming mode.
In FIG. 1, two typical sectors of a group of n sectors are shown, where the top sector is designated SECTOR 1 and the bottom sector is designated SECTOR n. Each sector is a array of memory cells formed from an array of EEPROM transistors, typically shown as a device 110 having a drain terminal D connected to a bit line B10, a control gate CG connected to a word line WLn, a floating gate, and a source terminal S.
The source terminals of all of the cells in a sector are connected together and through a source switch transistor 112 to a control line 114. Each sector has its own source line and a source selection line so that the source line goes up and down in voltage depending upon read, program and erase operations. During programming the source line needs to be plus five volts, which is controlled by the source switches which connect VCC or ground to the sources of the array. A decoder selects the sector to be programmed or erased by providing five volts on the control line 114. The other unselected sectors are kept at zero volts to keep them inactive. Sector n has a similar arrangement.
The negative charge pump voltage VNQP for erasing the cells of Sector 1 is provided from the dedicated charge pump 102 through diode-connected transistors 116, 118 to the various word lines for the cells of the sector. The diodes group several word lines together to form a sector. A group of word lines, for example, 16 or 32, form a sector. Note that each sector, or group of word lines, (1 through n) is driven by its own individual, dedicated charge pump, as shown. VNQP is -15 volts for an erase operation and -12 volts is then applied from the diode output terminals to the word lines WL0 through WLn of a sector.
The operation and structure of an EEPROM memory array where each sector has its own charge pump, such as described in connection with FIG. 1, is discussed in U.S. Pat. No. 5,077,691, issued Dec. 13, 1991, to Haddad et al.
Twin-well CMOS processes are well known for fabrication of EEPROMs and providing the appropriate voltages for programming, reading, and erasing typically requires using a number of dedicated charge pumps, each driving only one sector of the array.
A more complex, non-standard, fabrication process known as a triple-well process can be used to make the switching of positive and negative voltages possible. Adding a third well requires special equipment and manufacturing expertise. As a result, the triple-well process adds considerable complexity to a FLASH fabrication process and makes manufacturing more difficult.
Consequently, a need exists for a twin-well CMOS system which can provide the operational voltages for all of the different sectors of a negative-gate erase FLASH EEPROM array by using a single negative voltage supply and a single positive voltage supply for all of the sectors of the array and which can also provide a way to decode and steer the required voltages to the array.